The present invention relates to digital memories, and more particularly, to digital memories that are reconfigurable to replace selected defective memory elements with non-defective redundant memory elements for increased yield. In the context of the present invention, the term xe2x80x9cdigital memoriesxe2x80x9d include static Random Access Memories (RAMs), dynamic RAMs, Magnetic RAMs, registers, latches and any other type of memory or memory device.
It is common in the manufacture of large-area integrated circuit devices for defects to occur. This is particularly true for high density circuits, such as digital memories. To increase the yield of such circuits, it is common to include redundant circuit elements that can be used to replace the defective circuit elements. For example, in many memory devices, redundant columns and/or redundant rows are provided. During wafer level testing, the defective memory elements are identified, and the defective columns or rows are replaced with redundant columns or rows for increased yield.
To perform such a replacement, replacement circuitry is typically provided. The replacement circuitry is often programmed using one or more fuses. Thus, depending on the desired replacement, selected fuses are conditioned (e.g., blown), which causes the replacement circuitry to affect the desired replacement. For digital memories, the fuses and replacement circuitry are typically configured so that an individual memory element cannot be replaced. Rather, an entire row or column must be replaced.
Common integrated circuit fuses include laser blown, laser annealed, or electrically blown type fuses. To condition the fuses, direct access to the fuses is often required. For example, to condition a laser blown or laser anneal type fuse, a laser must have access to the fuse. To condition an electrically blown type fuse, a high voltage or current probe must often have access to the fuse. Because access is often required, the fuses must typically be conditioned before the integrated circuit is packaged, as the fuses are no longer accessible after packaging.
For many integrated circuits, significant post-packaging tests and procedures are performed to evaluate the performance and reliability of the packaged part. For example, it is common to perform burn-in, shake and bake, and other tests on the packaged parts before they are shipped to customers. If one or more memory elements fail during the post-packaging tests or procedures, the part is often discarded, as there is typically no effective way to access the fuses to perform further repairs. Likewise, if some of the memory elements fail after installed in a system, the part must typically be removed and replaced. This can be particularly problematic for many high reliability applications such as space applications and banking applications, where the part cannot be easily replaced and/or the system cannot go down because of part failure at unscheduled times.
The present invention overcomes many of the disadvantages of the prior art by providing a redundancy scheme for a memory that is programmable both before and after the device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved.
The present invention also contemplates a redundancy scheme that allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant row or single redundant column. This provides added flexibility during the replacement process, and may increase the number of defective memory elements that can be replaced with a limited number of redundant rows and/or redundant columns.
In a first illustrative embodiment of the present invention, a memory is provided that includes one or more memory elements and one or more redundant memory elements. A programmable replacement circuit is provided for replacing a selected memory element with a selected redundant memory element. The programmable replacing circuit preferably includes a non-volatile memory and is controlled, at least in part, by the value stored in the non-volatile memory. The programmable replacing circuit may use the value stored in the non-volatile memory to determine which of the redundant memory elements should be used to replace the selected memory element. Alternatively, or in addition, the programmable replacing circuit may use the value stored in the non-volatile memory element to determine which of the memory elements is selected for replacement by the selected redundant memory element.
For many digital memories, the memory elements are arranged in a number of rows and a number of columns. Each of the rows is addressed by a row address, and each of the number of columns is addressed by a column address. Typically, one or more redundant rows or redundant columns are provided, or both. When a number of redundant columns are provided, and in an illustrative embodiment, a multiplexer or the like may be provided for each column in the array. The multiplexer preferably selects between the output of the corresponding column in the array and the outputs of the one or more redundant columns.
The non-volatile memory may then control the selection of each multiplexer. For example, when a defective memory element is found in a first column of the array, the non-volatile memory may cause the first multiplexer to select the output of a first redundant column. Likewise, when a defective memory element is found in a second column of the array, the non-volatile memory may cause the second multiplexer to select the output of a second redundant column. In some cases, if the defective memory element in the first column is not in the same row as the defective memory element in the second column, the non-volatile memory may cause the first multiplexer and the second multiplexer to select the output of the same redundant column.
The selection of which redundant column to select may be controlled by a number of non-volatile memory elements, one for each multiplexer. The non-volatile memory elements may be directly coupled to the selection inputs of the multiplexers. Alternatively, the selection may be controlled by a programmable controller. For maximum flexibility, the controller may determine which redundant column to select based on the row address currently provided to the memory, and the location (e.g., row) of other defective bits. This flexibility may increase the number of defective memory elements that can be replaced with a limited number of redundant columns.
When a number of redundant rows are provided, it is contemplated that a number of non-volatile memory elements or a programmable controller with non-volatile memory may be provided. The non-volatile memory elements may be programmed to directly disable a defective row and enable a redundant row. When a programmable controller is provided, the programmable controller preferably controls which word line is activated during each memory access. In a typical memory, each row (including each redundant row) is controlled by a unique word line. Preferably, the programmable controller can identify which rows have at least one defective memory element. When one of these rows are accessed, the programmable controller activates a word line of one of the redundant rows to affect the desired replacement.
The programmable controller may include a lookup table using, at least in part, non-volatile memory elements. The programmable controller provides the row address to the lookup table. The value provided by the lookup table preferably controls the replacement circuitry. In one embodiment, if the row identified by the row address has a defective memory element, the value provided by the lookup table disables the word line of that row, and enables the word line of a selected redundant row. Likewise, if the row identified by the row address does not have a defective memory element, the value provided by the lookup table enables the word line of the row addressed by the row address, and does not enable the word line of any of the redundant rows.
Alternatively, or in addition to, the programmable controller may include non-volatile registers for storing the row addresses that have at least one defective memory element. A comparator or the like may then compare the row address that is provided to the memory with the row addresses stored in the non-volatile registers. If the current row address matches a row address stored in the non-volatile registers, the word line that corresponds to the current row address is disabled, and the word line of a selected redundant row is enabled. It is contemplated that the non-volatile registers may store an identifier for identifying which redundant row should be activated when the current row address matches a row address stored in the non-volatile registers.